1. Field of Invention
The present invention relates to a semi-conductor device. More specifically, the present invention relates to a non-volatile memory array.
2. Description of Related Art
Among various types of non-volatile memory products, electrically erasable programmable read-only memory (EEPROM) is a memory device that has been widely used in personal computers and electronic equipment. Data can be stored, read out or erased form the EEPROM many times, and the stored data are retained in the memory even after power supplying the device is cut off.
Typical EEPROM includes a floating gate and a control gate fabricated by doped polysilicon. The non-volatile memory includes a dual-layer gate, which is hard to integrate with a regular CMOS logic process. In addition, because of the dual-layer gate, the manufacturing cost of the entire embedded non-volatile memory is high that results in less competitive in the market.
In addition, when the memory has been programmed, the electrons injected in a floating gate may be evenly distributed in the entire polysilicon floating gate layer. However, if defects exist in a tunneling oxide layer beneath the polysilicon floating gate layer, a device leaking current is likely generated, and thus the reliability of the device is affected.
To solve the problem of the EEPROM device leaking current, some may substitute the polysilicon with a charge trapping material which, for example, is silicon nitride. Since the silicon nitride is capable of catching electrons and the electrons injected into the silicon nitride layer concentrate in some local region, the defects exist in the tunneling oxide layer become less sensitive. Hence, the device leaking current phenomenon is unlikely occurred. Moreover, commonly there is a silicon oxide layer respectively on top of and beneath the silicon nitride layer to form an oxide-nitride-oxide (ONO) composite layer.
On the other hand, to avoid data reading error due to over-erase/write while erase or write operation is performed to the typical EEPROM, a select transistor is connected on one side of the floating gate and the control gate, so that a two-transistor (2T) structure is formed. The memory programming and reading are controlled via the select transistor.
However, during the operation of the memory unit array of non-volatile memory unit with the 2T structure, under different biases, the problems that memory unit is mis-written or mis-erased because of programming disturbance (program disturbs) or erase disturbance (erase disturbs) may happen; these problems may lead to a lower reliability of the memory units.